Floating-point arithmetic operations are well-known. The benefit of such operations is derived from the manner in which the floating-point number is represented by two registers, one to store the fixed-point number itself, the mantissa, and the other to store the exponent of that number. The advantage of such representation is that it increases the range of numbers which a register can accommodate.
In floating-point addition/subtraction, unlike multiplication or division, the exponents of the two numbers must be equal before the operation can be performed. Consequently, the exponents of the two numbers to be added or subtracted must be compared. The difference between the two exponents then represents the amount to which one exponent will have to be increased and the amount to which the mantissa associated with that exponent will have to be shifted in order to compensate for the increased value of the exponent.
A brief example will easily explain this operation. Assume the subtraction of 0.1101 from 1.010. The floating point representation for these numbers is 0.1101.times.2.sup.0 and 0.1010.times.2.sup.1, respectively, wherein the 2 represents the base of the exponent, indicating that the numbers are represented as binary numbers. The subtraction of the exponents of these numbers indicates that the smaller exponent, associated with mantissa 0.1101, will have to be increased by one, and consequently the mantissa of that exponent will have to be shifted to the right by one, to compensate for the increase in the exponent. Consequently, the new floating point representation for 0.1101.times.2.sup.0 is 0.01101.times.2.sup.1. With the exponents now equal, the mantissas can be added or subtracted, depending upon the applicable function to be performed.
Floating-point numbers are generally stored in registers as normalized numbers. This means that the most significant bit of the mantissa has a non-zero value. Employing this method allows the most accurate value of a number to be stored in a register and allows a wide range of numbers to be represented since the value of the exponent of the floating-point number will compensate for any "padded" zeros required at the most significant bit locations of the number.
In view of the fact that floating-point numbers are stored as normalized numbers, after the addition or subtraction occurs, before the result can be stored, it must be normalized. This occurs by calculating the first left-most bit place in which a non-zero value appears. This value will indicate the number of bits the number will have to be shifted to the left, so that the most significant bit of the number has a non-zero value. This number also indicates the value to which the exponent must be decreased to compensate for the leftward shifts of the mantissa.
In the systems of the prior art, after the number has been normalized a one must be added to the least significant bit minus one location (LSB-1), known as adding a round bit, to approximate the true value of the LSB. For example, if the LSB-1 is one (1), adding a one to that location will result in carry into the LSB thus giving a better approximation for the true result. In the systems of the prior art, the one, known as the round bit, is added after the number is normalized. The problem with such a technique is that to add a one to the LSB-1 of the result, after normalization, requires a full addition process. When the addition or subtraction involves higher-order numbers such as 64-bits, a full addition stage for the addition of a one to the LSB-1 is very time consuming and slow. Such a time delay will result in a delay in sending the result of this floating-point arithmetic operation to the other elements in the processing system, and consequently can delay the execution of the next set of operations to be performed. With the increased speed upon which current computers operate, unnecessary delays can be crucial to the operations of the system.
Additionally, with current floating-point systems, there is often an additional delay associated with informing other elements of the central processor when the floating-point addition/subtraction is completed. This idle time is critical in the high technology computers being developed today which operate at such rapid speeds.
Therefore, there is currently a need in the rapidly developing computer industry to overcome these shortcomings and enable floating-point additions and subtractions to occur more rapidly and with the same degree of accuracy.
The prior art has attempted to overcome these problems by predicting the normalization amount early based on the amount the floating-point number is aligned. This theory is based on the fact that usually very large alignments result in small normalization shifts. However, the success of this approach is limited to the infrequent cases of large alignment and is useless for the case of small or no alignment shift. In addition, the prior art relies on normalized input operands to function correctly.